Semiconductor integrated circuit

ABSTRACT

There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S 2 ) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S 6 ) and a predetermined linearity condition (S 7 ).

CLAIM OF PRIORITY

The present application claims priority from Japanese patent applicationJP 2009-221900 filed on Sep. 28, 2009, the content of which is herebyincorporated by reference into this application.

FIELD OF THE INVENTION

The present invention relates to a test circuit (a Built In Self-Testcircuit, abbreviated to a BIST circuit) for evaluating a variable delaycircuit and a delay control circuit integrated in a semiconductordevice.

BACKGROUND OF THE INVENTION

A timing generator LSI for supplying a clock signal to an LSI tester isprovided with a variable delay circuit and outputs a clock signal with aphase according to a test timing. Since a timing generator circuit isequipped with a plurality of variable delay circuits to sufficientlyensure the accuracy and the variable delay range of a clock signal to beoutput therefrom, the timing generator circuit is a complicated one. Thedelay control circuit can perform a small current control by using adigital-to-analog conversion circuit (hereinafter referred to as DAC) toimprove the accuracy of delay and save electricity. An increase indegree of integration also increases the number of variable delaycircuits which can be mounted on one LSI. Accordingly, the number ofvariable delay circuits mounted on one timing generator LSI reachesabout several hundreds.

A ring oscillator is formed of variable delay circuits to measure itsoscillation frequency, ensuring the operation of circuits in such atiming generator LSI. JP-A-2000-180514 discusses an example in which,although the document has its purpose to calibrate the phase of anoutput clock signal, a signal output to the terminal of a signaltransmission route is fed back to the starting end thereof to form aclosed loop oscillation circuit, which is used to adjust timing.

US2007/0091701 discloses a test method using the DAC. US2007/0091701discusses that the operation confirmation of a transistor forcontrolling the current path of the DAC is performed by a functionaltest; however, the output current and voltage are outputted to anexternal tester.

SUMMARY OF THE INVENTION

Almost all of test time for a delay circuit is spent for measurement bya frequency counter. The time required for the test depends on accuracyand oscillation frequency. Measurement time is on the order of severalmilliseconds to several seconds per circuit. The test time increases inproportion to measurement accuracy, the number of variable delaycircuits to be measured, and the number of combinations of delayadjustment parameters. As described above in “BACKGROUND OF THEINVENTION,” these factors are being increased. On the other hand, pinsfor test are increased in number to increase in the speed of input andoutput between a tester and an LSI, allowing reducing the test time,however, the number of pins allocated to the test is limited, whichcannot really suppress an increase in the time required for the test.

According to one aspect of the present invention, there is provided asemiconductor integrated circuit includes: a variable delay circuit; anda test circuit for the variable delay circuit; wherein the test circuitforms a ring oscillator using the variable delay circuit, causes thering oscillator to oscillate at the time of test operation anddetermines whether the variable delay circuit is normal or abnormaldepending on whether the ring oscillator satisfies predeterminedmonotonic increase and linearity conditions.

According to another aspect of the present invention, there is provideda semiconductor integrated circuit includes: a variable delay circuit; adelay control circuit including a digital analog conversion circuitconfigured to convert a digital signal to the amount of current andcontrolling the delay of the variable delay circuit by voltage accordingto the amount of current; and a test circuit for the delay controlcircuit; wherein the delay control circuit includes a plurality of unitcurrent sources selected according to the value of a digital signal andthe test circuit functionally and digitally determines that the value ofa current flowing into each of the plurality of the unit current sourcesfalls within a predetermined range to determine whether the delaycontrol circuit is normal or abnormal.

The time required for the test of the variable delay circuit and theanalog characteristic of the DAC is reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a variable delay circuit and a delay testcircuit therefor;

FIG. 2 is a flow chart of a test using FIG. 1;

FIG. 3 is a schematic diagram for a linearity evaluation determinationof the variable delay circuit;

FIG. 4 is a block diagram of the delay test circuit applied to aplurality of the variable delay circuits;

FIG. 5 is a block diagram of a delay control circuit and a test circuittherefor;

FIG. 6 is a diagram showing a generation probability of current flowing,into a unit current source;

FIG. 7 is a diagram showing a relationship among current, voltage, anddetermination output in a window comparator;

FIG. 8 is a circuit diagram in which the same control DAC is used as areplica DAC;

FIG. 9 is an example of a configuration in which test results areintegrated and output;

FIG. 10 is an example of a configuration in which a current switch ismounted; and

FIG. 11 is an example of a configuration of the variable delay circuitand the delay control circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

The test circuit and the test method of the variable delay circuit aredescribed below as a first embodiment.

FIG. 1 shows a block diagram of a variable delay circuit 100 to bemeasured and a delay test circuit therefor. The variable delay circuit100 delays an input signal by a delay according to a control signal froma delay control circuit 150. The blocks excluding the variable delaycircuit 100 are referred to as the delay test, circuit and include astate machine 200, a test switching circuit 300, a frequency measurementcircuit 400, a frequency counter register 500, an expected valuegenerating circuit 600, an expected value register 700, a comparisoncircuit 800, and a test result register 900.

In a normal operation mode, the test switching circuit 300 selects aclock signal SIG. The delay control circuit 150 receives a delay controlsignal to adjust a delay control parameter. The variable delay circuit100 delays the clock signal SIG input from delay control circuit 150according to a change in the delay control parameter and outputs thedelayed clock signal SIGOUT.

The flow on the whole of the test is described later with reference toFIG. 2. The function and the operation of each block are describedbelow.

A test setting signal is inputted into the state machine 200. The statemachine 200 includes a setting storage register 210 and a settingcontrol machine 220. Test setting data is scanned in the setting storageregister 210 from the outside. The setting control machine 220 receivessetting data from the setting storage register 210 and controls thedelay test circuit.

The test switching circuit 300 is controlled by the setting controlmachine 220 and selects a loop path L passing through the variable delaycircuit 100 at the time of starting the test, thereby forming a ringoscillator.

The frequency measurement circuit 400 includes a ring oscillator counter410 and a reference clock counter 420. The ring oscillator counter 410counts the number of times of oscillation of the ring oscillator whenthe test switching circuit 300 forms the ring oscillator. The referenceclock counter 420 counts the number of times of oscillation of areference clock. When the count value of the reference clock counter 420reaches a setting value given by the setting control machine 220, thereference clock counter 420 stops counting and stores the count value.At the same time, the count of the ring oscillator is ended.

The test of the variable delay circuit 100 is conducted using the countvalue of the ring oscillator counter 410 obtained when the count valueof the reference clock counter 420 reaches the predetermined settingvalue. Hereinafter, the count value of the ring oscillator counter 410is represented by C_(N) at the time (represented by time P_(N)) when thereference clock counter 420 reaches N-th predetermined setting valueafter the test starts. The counter register 500 stores the count valueof the ring oscillator counter 410, i.e., C_(N−1) at the time(represented by time P_(N−1)) when the reference clock counter 420reaches (N−1)th predetermined setting value.

The expected value generating circuit 600 uses the count value (C_(N))of the ring oscillator counter 410 and the count value (C_(N−1)) of thecounter register 500 to generate an expected value at the time of test.

The expected value register 700 includes a monotonic expected valueregister 710, a first linear expected value register 730, and a secondlinear expected value register 720. The monotonic expected valueregister 710 reads the count value stored in the counter register 500and stores it. The first linear expected value register 730 stores theexpected value E_(N+1), L_(uN+1), and L_(1N+1)) generated in theexpected value generating circuit 600. The second linear expected valueregister 720 reads an expected value (E_(N), L_(uN), and L_(1N)) beingearlier by one period than the expected value (E_(N+1), L_(uN+1), andL_(1N+1)) from the first linear expected value register 730 and storesthe expected value (E_(N), L_(uN), and L_(1N)).

The comparison circuit 800 compares the count value stored in the ringoscillator counter 410 with the expected value stored in the monotonicexpected value register 710 and the second linear expected valueregister 720.

The test result register 900 stores the comparison result from thecomparison circuit 800.

FIG. 2 is an example of the flow of a delay time test conducted in thecircuit shown in FIG. 1. The monotonic increase and linearity of delayof the variable delay circuit 100 are confirmed. The test of thevariable delay circuit 100 is narrowed to the evaluation of monotonicincrease and linearity to allow incorporating the expected valuegenerating circuit and a determination circuit into the LSI.

In step S1, the external tester writes test setting data into thesetting storage register 210. The setting control machine 220 reads thesetting data from the setting storage register 210 to execute thecontrol in step S2 and the subsequent steps.

In step S2, the test switching circuit 300 selects the loop path L toform the ring oscillator including the variable delay circuit 100 andcauses the ring oscillator to oscillate.

In step S3, the ring oscillator counter 410 and the reference clockcounter 420 start measuring count. When the count value of the referenceclock counter 420 reaches the setting value provided by the settingcontrol machine 220, the reference clock counter 420 outputs a countstop signal to the setting control machine 220. The setting controlmachine 220 receives the count stop signal and outputs the count stopsignal to the ring oscillator counter 410 to stop the ring oscillatorfrom counting. The count value C_(N) is stored in the ring oscillatorcounter 410 and measurement is ended.

In step S4, the expected value generating circuit 600 reads the countvalue C_(N) stored in the ring oscillator counter 410 and the countvalue C_(N−1) stored in the counter register 500, generates the linearexpected value E_(N+1) and defines a linearity determination range.

FIG. 3 shows a schematic diagram for a linearity evaluationdetermination. In FIG. 3, the abscissa denotes time and the ordinatedenotes the count value of the ring oscillator counter 410. If thedifference between the count values C_(N) and C_(N−1) is take as Δ, theexpected value E_(N+1) of the count value at the time P_(N−1) can berepresented by C_(N)+Δ. The linearity determination range within whichthe output of the variable delay circuit 100 at the time P_(N+1) isregarded as satisfying linearity is expressed by the following equationsusing a linearity allowance range R provided by the setting controlmachine 220:

L _(uN+1) =E _(N+1) +R

L _(1N+1) =E _(N+1) −R

where L_(uN+1) is the upper limit value of the linearity determinationrange at the time P_(N+1) and L_(1N+1) is the lower limit value thereof.The values are stored in the first linear expected value register 730.

In step S5, the count value C_(N−1) stored in the counter register 500is read into the monotonic expected value register 710 and taken as anexpected value to be used for monotonic evaluation.

In step S6, the comparison circuit 800 compares the count value C_(N−1)stored in the monotonic expected value register 710 with the count valueC_(N) stored in the ring oscillator counter 410. If C_(N−1)<C_(N), it isdetermined that the count value C_(N) monotonically increases. After thecomparison is ended, the test result is stored in the test resultregister 900. If it is determined that the count value C_(N)monotonically increases, the proceeding proceeds to the following stepfor linearity evaluation. If it is determined that the count value C_(N)does not monotonically increase, the result is outputted and theprocessing is ended (step S11).

In step S7, the comparison circuit 800 reads the upper limit valueL_(uN) and the lower limit value L_(1N) of the linearity determinationrange stored in the second linear expected value register 720 and thecount value C_(N) stored in the ring oscillator counter 410 and ifL_(1N)<C_(N)<L_(uN), it is determined that the count value C_(N) iswithin a prescribed linearity range. If the linearity comparison issatisfied, it is confirmed whether the parameter is the latest one. Ifit is confirmed that the parameter is not the latest one, the result isoutputted and the proceeding is ended (step S11).

In step S8, if the control parameter is the latest one, the result isoutputted and the proceeding is ended (step S11). If the controlparameter is not the latest one, the count value C_(N) stored in thering oscillator counter 410 is stored in the counter register 500. Theexpected value (E_(N+1), L_(uN+1) and L_(1N+1)) stored in the firstlinear expected value register 730 is stored in the second linearexpected value register 720 (step S9). After storage, the time parameteris changed from N to (N+1) in step S10, and measurement is continued.

FIG. 4 shows an example of configuration of a plurality of the variabledelay circuits 100. The blocks being common in function to those in FIG.1 are denoted by the same reference characters and numerals. FIG. 4 hastwo variable delay circuits. The blocks and the signals related to afirst variable delay circuit 100 a are provided with a subscript “a” andthe blocks and the signals related to a second variable delay circuit100 b are provided with a subscript “b,” the detailed descriptionthereof is omitted. Thus, a test switching circuit 310 corresponding tothe variable delay circuit, a frequency measurement circuit 400 and thelike are prepared for the plurality of the variable delay circuits 100to allow simultaneous test of a plurality of the variable delaycircuits. Thereby, testing time can be reduced.

In the configuration of FIG. 4, an inverter 1000 is put between a firstvariable delay circuit 100 a and a second variable delay circuit 100 bto couple them together, thereby allowing forming a ring oscillatorusing two variable delay circuits. The selector of the test switchingcircuit 310 switches three inputs. In a normal operation mode, the clocksignal SIG input to an input in1 is inputted. If a plurality of thevariable delay circuits is separately tested, the selector selects aninput in2. In this case, each of the variable delay circuits is testedas is the case with the example in FIG. 1. When the selector selects aninput in3, a loop path of the variable delay circuit 100 a, the inverter1000, the test switching circuit 310 b, the variable delay circuit 100b, and the test switching circuit 310 a is formed to form a ringoscillator using two variable delay circuits 100 a and 100 b.

A small delay of the variable delay circuit increases the oscillationfrequency of the ring oscillator, which makes it difficult to conduct atest. As shown in FIG. 4, the ring oscillator is formed by a pluralityof the variable delay circuits to suppress the increase of theoscillation frequency of the ring oscillator even if an individualvariable delay circuit is small in delay, increasing the accuracy of atest. Furthermore, the delays of the first and the second variable delaycircuit are complementarily changed to make constant the oscillationfrequency of the coupled ring oscillator, enabling the influence offrequency dependency to be eliminated, which allows further increasingtest accuracy.

Second Embodiment

In the second embodiment, the test circuit and the test method of thedelay control circuit 150 are described below. In a configuration inFIG. 5, delay is controlled by the DAC. A control DAC 2100 has aplurality of unit current sources M1 to M3. The control. DAC 2100performs switching between conduction and non-conduction of transistorsM4 to M6 using control signals DC1 to DC3. Current I_(D) flowingaccording to a control DAC control signal DC is current/voltageconverted by a mirror circuit MR1 and a voltage according to the currentI_(D) is applied to the variable delay circuit 100 to control the delay.It is needless to say that the number of unit current sources of thecontrol DAC 2100 is not limited to three. The gate width W of each ofthe unit current sources M1 to M3 may be adjusted to make the currentI_(D) multiple. In the present embodiment, it is tested whether all bitsin the control DAC 2100 normally operate using the output current of thecontrol DAC. “All bits normally operate” means that both of thefollowing are satisfied: conduction and non-conduction of thetransistors M4 to M6 are normally performed; and current flowing intothe unit current sources M1 to M3 falls within a design value.

Thus, a test for each unit current source is conducted instead ofconducting a test for all variable delay parameters in the delay controlcircuit to allow reducing the number of tests from the number of allvariable delay parameters to the number of unit current sources in thedelay control circuit, enabling the test time to be reduced. Since themagnitude relation between the amounts of current in the unit currentsources can be directly tested with respect to a change in delay in thevariable delay circuit, measurement accuracy can be improved.

A test circuit for the delay control circuit 150 is formed of a replicaDAC 2200 and a window comparator 2300.

The replica DAC 2200 also includes a plurality of unit current sourcesM11 to M13. Replica DAC control signals RDC1 to RDC3 perform switchingbetween conduction and non-conduction of transistors M14 to M16. Thecommon reference voltage is applied to the gates of the unit currentsources of the control DAC 2100 and the replica DAC 2200. It isnecessary only that the replica DAC 2200 can cause current I_(R)required for the test for the control DAC 2100 to flow, so that thereplica DAC 2200 does not always need to be similar in configuration tothe control DAC 2100. Since the replica DAC 2200 is mounted in the sameLSI, the replica DAC 2200 is desirably as small as possible to reduceoverhead.

The window comparator 2300 includes a window width adjustment circuit2310 and a determination circuit (an OR circuit in this example) 2320.

The window width adjustment circuit 2310 is controlled by window widthsetting signals WS1 and WS2. A current mirror circuit draws a currentequivalent to the output current I_(D) of the control DAC 2100 andtransistors M21 and M22 the size of which is adjusted to the currentadjust an output current I_(w).

An example is shown below. Suppose that the current I_(D) is mirrored onthe source and drain path of the transistor M21 when the gate width ofthe transistor M21 is w. In this case, the gate width of the transistorM21 is taken as 0.8 w and the gate width of the transistor M22 is 0.4 w.At this point, both of the transistors M21 and M22 are caused to conductto obtain the output current I_(w)=1.2 I_(D). The transistor M21 iscaused to conduct and the transistor M22 is not caused to conduct toobtain the output current I_(w)=0.8 I_(D).

The determination circuit 2320 determines whether a current in which theoutput current of the control DAC 2100 is adjusted by the window widthadjustment circuit 2310 is greater or smaller than the output current ofthe replica DAC 2200.

The window width setting signal WS, the control DAC control signal DC,the replica DAC control signal RDC, and a test enable TE are inputtedfrom the outside (tester).

The determination principle of the window comparator 2300 is describedbelow with reference to FIGS. 6 and 7 with the unit current source M1 ofthe control DAC 2100 as an example. When the transistor M4 is caused toconduct and the transistors M5 and M6 are caused not to conduct, it issupposed that the current I_(D) (actual measured value) flows into theunit current source M1.

As shown in FIG. 6, the current I_(D) flowing into the unit currentsource M1 disperses with a design value I_(DI) as a center, so that ifthe actual measured value is within the range of the following formula(1), the unit current source M1 is regarded as being normally operated:

b·I _(DI) <I _(D)(actual measured value)<a·I _(DI)(a>1,0≦b≦1)  (1).

In the configuration in FIG. 5, a determination is made as describedbelow as to whether the current I_(D) (actual measured value) fallswithin a predetermined normal range.

[Determination of Upper Limit]

As shown in FIG. 6, if the current I_(D) is represented by the followingformula (2):

k ₁ ·I _(D) <a·I _(DI)(a>k ₁>1)  (2)

the upper limit is regarded as being satisfied. For the sake ofsimplicity of description, suppose that the output current I_(R) of thereplica DAC is equal to I_(DI) (that is, I_(R)=I_(DI)). For example, theunit current source M1 of the control DAC and the unit current sourceM11 of the replica DAC are produced by transistors with the same size tosatisfy the supposition.

Therefore, the formula (2) can be replaced by the following formula (3):

k ₁ ·I _(D) <a·I _(R)(a>k ₁>1)  (3).

The formula (3) is transformed to the following formula (4):

(k ₁ /a)·I _(D) =K ₁ ·I _(D) <I _(R)(K ₁<1)  (4).

For this reason, if the parameter of the window width adjustment circuit2310 is the output current

I _(w) =K ₁ ·I _(D) ,I _(w) <I _(R)  (5),

when the relationship represented by of the formula (5) is satisfied, itcan be determined that the upper limit is satisfied.

[Determination of Lower Limit]

As shown in FIG. 6, suppose that the following formula (6) satisfies theupper limit:

B·I _(DI) <k ₂ ·I _(D)′(1>k ₂ >b>0)  (6).

Similarly, if it is supposed that the output current I_(R) of thereplica DAC is equal to I_(DI) (that is, I_(R)=I_(DI)), the formula (6)can be replaced by the following formula (7):

b·I _(R) <k ₂ ·I _(D)′(1>k ₂ >b>0)  (7).

The formula (7) is transformed to the following formula (8):

I _(R)<(k ₂ /b)·I _(D) ′=K ₂ ·I _(D)′(K ₂>1)  (8).

For this reason, if the parameter of the window width adjustment circuit2310 is the output current I_(w)′=K₂·I_(D)′,

I_(R)<I_(w)′  (9),

when the relationship represented by the formula (9) is satisfied, itcan be determined that the lower limit is satisfied.

FIG. 7 shows the relationship between current and voltage in the windowcomparator 2300. In the determination of the upper limit, the currentI_(w) adjusted so that the output current I_(D) of the control DAC 2100is reduced by the window width adjustment circuit 2310 and the outputcurrent I_(R) of the replica DAC 2200 is in an equilibrium state at thecurrent I. The voltage at a node Vc at this point is taken as V₁. In thedetermination of the lower limit, the current I_(w)′ adjusted so thatthe output current I_(D)′ of the control DAC 2100 is increased by thewindow width adjustment circuit 2310 and the output current I_(R) of thereplica DAC 2200 is in an equilibrium state at the current I′. Thevoltage at a node Vc at this point is taken as V₂.

The window comparator 2300 determines whether the output current I_(R)of the replica DAC and the currents I_(w) and I_(w)′ corresponding tothe upper and the lower limit respectively have the relationship shownin FIG. 7. The OR circuit in the determination circuit 2300 functions asan inverter if the test enable TE is Low and compares the voltageappearing at the node Vc with a logic threshold voltage V_(TH) of the ORcircuit. If the currents I_(R), I_(w), and I_(w)′ have the relationshipshown in FIG. 7, in the determination of the upper limit, the nodeVc=V₁<V_(TH), so that the determination result becomes “Low.” In thedetermination of the lower limit, the node Vc=V₂>V_(TH), so that thedetermination result becomes “High.” If the above determination resultsappear in the determination of the upper and the lower limit, it isdetermined that the unit current source M1 of the control DAC 2100 isnormally operated. At this point, the determination of the unit currentsource M1 is completed and then the determination of the unit currentsource M2 is started. Thus, the test of the control DAC is digitallydetermined to produce an effect in which a logic test of a general LSItest and an interface can be made common.

FIG. 8 shows an example of a configuration in which the control DAC ofthe delay control circuit existing in the same LSI is used as a replicaDAC of a different delay control circuit. In the example of FIG. 8, acontrol DAC 2100 b for a variable delay circuit 100 b is used as areplica DAC for a control DAC 2100 a. A control DAC 2100 c for avariable delay circuit 100 c is used as a replica DAC for a control DAC2100 b. A control DAC 2100 a for a variable delay circuit 100 a is usedas a replica DAC for a control DAC 2100 c. The control DACs 2100 aresimilar in configuration to each other. A window comparator 6100includes a window width adjustment circuit 6110, a determination circuit6120, and a switch circuit 6130. Although the window width adjustmentcircuit 6110 is different in polarity from the window width adjustmentcircuit shown in FIG. 5, the window width adjustment circuit 6110functions similarly therewith. In a test operation mode (the test enableTE is low), the switch circuit 6130 conducts to operate the window widthadjustment circuit 6110. In a normal operation mode (the test enable TEis high), the switch circuit 6130 does not conduct, causing the windowwidth adjustment circuit 6110 not to operate.

The unit current source of the control DAC 2100 a is tested such thatthe electric potential at the node V_(c1) determined by the amount ofcurrent in which the current flowing into the control. DAC 2100 a isadjusted for the upper/lower determination by the window widthadjustment circuit 6110 a and the amount of current flowing into thecontrol. DAC 2100 c (the replica DAC) is determined by a determinationcircuit 6120 a. The unit current source of the control DAC 2100 b istested such that the electric potential at the node V_(c2) determined bythe amount of current in which the current flowing into the control DAC2100 b is adjusted for the upper/lower determination by the window widthadjustment circuit 6110 b and the amount of current flowing into thecontrol DAC 2100 b (the replica DAC) is determined by a determinationcircuit 6120 b. The unit current source of the control DAC 2100 c istested such that the electric potential at the node V₃ determined by theamount of current in which the current flowing into the control DAC 2100c is adjusted for the upper/lower determination by the window widthadjustment circuit 6110 c and the amount of current flowing into thecontrol DAC 2100 b (the replica DAC) is determined by determinationcircuit 6120 c. An example where unit current sources M61, M71, and M81are tested is described below. Control signals DC3_a, DC3_b, and DC3_care rendered to be high to cause the transistors M62, M72, and M82 toconduct. Other control signals DC1 and DC2 are rendered to be low tocause current to flow into the control DACs 2100 a to 2100 c accordingto the unit current sources M61, M71, and M81 respectively. Thus, theunit current source of the control DAC 2100 is tested.

Thus, the control DAC with the same configuration regarded as thereplica DAC is used to allow preventing the area overhead of the testcircuit from being increased. In the example of FIG. 8, although threecontrol DACs are used, the present invention is not limited to thisnumber.

FIG. 9 shows an example of a configuration in which the determinationresults of a plurality of the variable delay circuits are collectivelyoutput and determined. In FIG. 9, the delay control circuit 150corresponding to one variable delay circuit 100 and the test circuitsthereof are referred to as one test unit.

In this example, there are included an AND circuit 4400, an OR circuit4500, and a selector 4600 to which determination results are inputtedfrom the window comparators 2300 of a plurality of test units 4000 and aselector 4700 for selecting outputs of the AND circuit 4400, the ORcircuit 4500, and the selector 4600.

As a description is made in relation to FIG. 7, the output of the windowcomparator 2300 being Low in the determination of the upper limit of theunit current source and the output of the window comparator 2300 beingHigh in the determination of the lower limit of the unit current sourceare an expected value in a normal operation mode. In the determinationof the upper limit of the unit current source, the selector 4700 selectsthe OR circuit 4500. If even one High output exists in the determinationresult from the test unit, the output result becomes High, so that itcan be determined that the test unit deviating from the expected valueexists. On the other hand, in the determination of the lower limit ofthe unit current source, the selector 4700 selects the AND circuit 4400.If even one Low output exists in the determination result from the testunit, the output result becomes Low, so that it can be determined thatthe test unit deviating from the expected value exists.

The selector 4600 is used when the determination result is separatelyoutput from each test unit as a debug mode if the integrateddetermination result is not obtained as expected from the selector 4700.

It is needless to say that the number of the test units is not limitedto four. Each test unit may use the configuration shown in FIG. 5 or 8.

FIG. 10 is an example of configuration for increasing a test accuracy,in which a current switch is used. A MOS transistor increases in aproduction dispersion along with the miniaturization thereof, whichdisperses the characteristics thereof. The influence of the dispersioncan be reduced by increasing the gate length (Lg) of the MOS transistor.A transistor M31 forming a current source 5100 for supplying a controlvoltage to the variable delay circuit 100 in a normal operation mode isformed of a miniaturized MOS transistor matched to a transistor in thevariable delay circuit 100. This is because a small change in current ina saturation area is desired to improve sensitivity at the time ofcomparing current. For this reason, the transistor M31 is configuredwith the gate length equal to that of the MOS transistor forming thevariable delay circuit 100. In FIG. 5, the power supply NMOS (thetransistors M11, M12, and M13 of the replica DAC 2200) and the powersupply PMOS (the transistors M23, M24, and M25 of the window widthadjustment circuit 2310) correspond to the above. On the other hand, aMOS transistor shows a great change in current in the saturation areaalong with the miniaturization thereof. It is desirable that a change incurrent in the saturation area is small as the MOS transistor of thewindow comparator 2300, which may worsen sensitivity. A current sourceM32 greater in size, that is to say, greater in a gate length (Lg) thanthe transistor M31 of a current source 5100 receiving the output of thecontrol DAC used in the normal operation mode is used at the time oftest to use the power supply excellent in characteristic, improving thedetermination accuracy of the determination circuit.

The configuration of FIG. 10 is different from that of FIG. 5 in thatthe output current of the replica DAC 2200 is switched between the upperlimit determination and the lower limit determination by a window widthadjustment circuit 5210. It can be determined whether the unit currentsource is normally operated based on the same principle as those ofFIGS. 6 and 7.

In the example of the present configuration, a current switching circuitreceiving the test enable TE is provided. In a normal operation mode,that is to say, in the case where the test enable TE is High, thetransistors M43 and M44 conduct to output a delay control signalaccording to the delay control signal DC. On the other hand, thetransistors M41 and M42 are caused not to conduct.

At the time of test, the test enable TE is rendered to be Low to causethe transistors M43 and M44 not to conduct and the transistors M41 andM42 to conduct. Thereby, the voltage at the node V_(c) determined by themagnitude relation between the output current I_(X) obtained byswitching the mirror output current I_(RM) of the replica DAC 2200 bythe window width adjustment circuit 5210 and the mirror output currentI_(RM) of the control DAC 2100 is determined by the determinationcircuit 5220 and the determination result is outputted.

The invention made by the inventors is described above based on theembodiments. It is needless to say that the present invention is notlimited to the embodiments and various changes may be made withoutdeparting from the sprit and scope of the present invention. FIG. 11shows an example of configuration of the variable delay circuit 100 andthe delay control circuit 150. The delay control circuit 150 controlsthe delay of the variable delay circuit 100 by controlling the ONresistance of the NMOS transistor M51 provided between the delay element6000 and the reference electric potential and the PMOS transistor M52provided between the delay element 6000 and the power supply electricpotential.

The present invention is applicable not only to a circuit having eitherthe variable delay circuit or the DAC, but to a circuit having both thevariable delay circuit and the DAC. The output of the variable delaycircuit may be output by fine adjusting the clock signal coarse adjustedby a first variable delay circuit by a second variable delay circuitinstead of outputting the output of the variable delay circuit, as itis. It is to be understood that the DAC to which the test circuitdescribed in the embodiments can be applied is not limited to the DACused for the delay control circuit.

1. A semiconductor integrated circuit comprising: a variable delaycircuit; and a test circuit for the variable delay circuit; wherein thetest circuit forms a ring oscillator using the variable delay circuit,causes the ring oscillator to oscillate at the time of test operationand determines whether the variable delay circuit is normal or abnormaldepending on whether the ring oscillator satisfies predeterminedmonotonic increase and linearity conditions.
 2. The semiconductorintegrated circuit according to claim 1, wherein the test circuit storesa first count value of the ring oscillator at a first time and a secondcount value of the ring oscillator at a second time after apredetermined time elapsed from the first time and determines that thering oscillator satisfies the monotonic increase condition when therelation of the first count value<the second count value is satisfied.3. The semiconductor integrated circuit according to claim 1, whereinthe test circuit stores a first count value of the ring oscillator at afirst time, a second count value of the ring oscillator at a second timeafter a predetermined time elapsed from the first time and a third countvalue of the ring oscillator at a third time after a predetermined timeelapsed from the second time and determines that the ring oscillatorsatisfies the linearity condition if a deviation between the third countvalue and an expected count value at the third time expected from thesecond count value and the increment of count value of the ringoscillator at the first to the second time falls within a predeterminedrange.
 4. A semiconductor integrated circuit comprising: a firstvariable delay circuit; a first switching circuit configured to switchan input to the first variable delay circuit by an external input and anoutput from the first switching circuit; a ring oscillator counterconfigured to count the output of a ring oscillator formed by the firstswitching circuit selecting the output from the first variable delaycircuit and output a count value at a predetermined timing; a firstregister configured to store the count value preceding by one countvalue output by the ring oscillator counter; and a second registerconfigured to predict an expected count value which the ring oscillatorcounter is expected to output from the past count value of the ringoscillator counter and store the expected count value; wherein the countvalue output by the ring oscillator is compared with the count valuestored into the first register and the expected count value stored intothe second register to determine whether the first variable delaycircuit is normal or abnormal.
 5. The semiconductor integrated circuitaccording to claim 4, wherein if the count value output by the ringoscillator is greater than the count value stored into the firstregister and a deviation between the count value output by the ringoscillator and the expected count value is equal to or smaller than apredetermined value, it is determined that the first variable delaycircuit is normal.
 6. The semiconductor integrated circuit according toclaim 4, further comprising: a second variable delay circuit; and asecond switching circuit configured to switch an input to the secondvariable delay circuit by an external input and outputs from the firstand the second variable delay circuit; wherein the first switchingcircuit is configured to enable selecting the output of the secondvariable delay circuit and the ring oscillator counter counts the outputof a ring oscillator including the first and the second variable delaycircuit when the first switching circuit selects an output from thesecond variable delay circuit and the second switching circuit selectsan output from the first variable delay circuit.
 7. The semiconductorintegrated circuit according to claim 6, wherein the delay of the firstvariable delay circuit and the delay of the second variable delaycircuit are complementarily changed to determine whether the variabledelay circuit is normal or abnormal.
 8. A semiconductor integratedcircuit comprising: a first variable delay circuit; a first delaycontrol circuit including a first digital analog conversion circuitconfigured to convert a digital signal to the amount of current andcontrolling the delay of the first variable delay circuit by voltageaccording to the amount of current; and a first test circuit for thefirst delay control circuit; wherein the first digital analog conversioncircuit includes a plurality of unit current sources selected accordingto the value of a digital signal and the first test circuit determinesthat the value of a current flowing into each of the plurality of theunit current sources falls within a predetermined range to determinewhether the first delay control circuit is normal or abnormal.
 9. Thesemiconductor integrated circuit according to claim 8, furthercomprising: a second variable delay circuit; a second delay controlcircuit including a second digital analog conversion circuit configuredto convert a digital signal to the amount of current and controlling thedelay of the second variable delay circuit by voltage according to theamount of current; and a second test circuit for the second delaycontrol circuit; wherein the second digital analog conversion circuitincludes a plurality of unit current sources selected according to thevalue of a digital signal and the second test circuit determines whetherthe value of a current flowing into each of the plurality of the unitcurrent sources falls within a predetermined range to determine whetherthe second delay control circuit is normal or abnormal.
 10. Thesemiconductor integrated circuit according to claim 9, wherein thedetermination results of the first and the second delay control circuitare outputted with the determination results integrated.
 11. Thesemiconductor integrated circuit according to claim 9, wherein the firsttest circuit includes a current adjustment circuit configured toincrease or decrease the amount of current of the second digital analogconversion circuit by a predetermined amount, and wherein the amount ofcurrent flowing into the first digital analog conversion is comparedwith a first amount of current in which the amount of current flowinginto the second digital analog conversion is increased by the currentadjustment circuit by a predetermined amount and a second amount ofcurrent in which the amount of current flowing into the second digitalanalog conversion is decreased by the current adjustment circuit by apredetermined amount to determine whether the value of current flowinginto the unit current source falls within a predetermined range.
 12. Thesemiconductor integrated circuit according to claim 9, wherein the firsttest circuit includes a current adjustment circuit configured toincrease or decrease the amount of current of the first digital analogconversion circuit by a predetermined amount, and wherein the amount ofcurrent flowing into the second digital analog conversion is comparedwith a first amount of current in which the amount of current flowinginto the first digital analog conversion is increased by the currentadjustment circuit by a predetermined amount and a second amount ofcurrent in which the amount of current flowing into the first digitalanalog conversion is decreased by the current adjustment circuit by apredetermined amount to determine whether the value of current flowinginto the unit current source falls within a predetermined range.
 13. Thesemiconductor integrated circuit according to claim 8, wherein the firsttest circuit includes a third digital analog conversion circuitconfigured to convert a digital signal to the amount of current and acurrent adjustment circuit configured to increase or decrease the amountof current of the third digital analog conversion circuit by apredetermined amount, and wherein the amount of current flowing into thefirst digital analog conversion is compared with a first amount ofcurrent in which the amount of current flowing into the third digitalanalog conversion is increased by the current adjustment circuit by apredetermined amount and a second amount of current in which the amountof current flowing into the second digital analog conversion isdecreased by the current adjustment circuit by a predetermined amount todetermine whether the value of current flowing into the unit currentsource falls within a predetermined range.
 14. The semiconductorintegrated circuit according to claim 8, wherein the first test circuitincludes a third digital analog conversion circuit configured to converta digital signal to the amount of current and a current adjustmentcircuit configured to increase or decrease the amount of current of thefirst digital analog conversion circuit by a predetermined amount, andwherein the amount of current flowing into the third digital analogconversion is compared with a first amount of current in which theamount of current flowing into the first digital analog conversion isincreased by the current adjustment circuit by a predetermined amountand a second amount of current in which the amount of current flowinginto the first digital analog conversion is decreased by the currentadjustment circuit by a predetermined amount to determine whether thevalue of current flowing into the unit current source falls within apredetermined range.